EE 2000 - Digital Design with HDL

Credit Hour(s): 3
Introduction to combinational and synchronous sequential digital system design and optimization. Use of structural hardware description language (HDL) with CAD tools for design and simulation in a field programmable gate array (FPGA) based laboratory environment. Design and testing of simple combinational and synchronous sequential circuits.
Prerequisite(s): WSU Math Placement Level 30 or Undergraduate level MTH 1280 Minimum Grade of C or Undergraduate level MTH 1350 Minimum Grade of C or Undergraduate level MTH 2300 Minimum Grade of C
Corequisite(s): EE2000L
Enrollment Restrictions: Must be enrolled in one of the following Colleges: College of Egr & Computer Sci.

Level: Undergraduate
Schedule Type(s): Lecture