CEG 7030L - VLSI Design Synthesis and Optimization Laboratory

Credit Hour(s): 1
Required laboratory for EE 7530. Department Managed Prerequisite(s): (Undergraduate level EE 4620 Minimum Grade of D and Undergraduate level EE 4620L Minimum Grade of D) or (Graduate level EE 6620 Minimum Grade of D and Graduate level EE 6620L Minimum Grade of D)
Corequisite(s): CEG7030
Enrollment Restrictions: Must be enrolled in one of the following Levels: Graduate, Medical, Professional.

Level: Graduate
Schedule Type(s): Lab