CEG 7030 - VLSI Design Synthesis and Optimization

Credit Hour(s): 3

Course Description: VLSI Synthesis and optimization including data path synthesis, glue logic synthesis control-unit synthesis, and resource sharing. Covers behavioral level to layout level synthesis and corresponding algorithms. Department Managed Prerequisite(s): (Undergraduate level EE 4620 Minimum Grade of D and Undergraduate level EE 4620L Minimum Grade of D) or (Graduate level EE 6620 Minimum Grade of C and Graduate level EE 6620L Minimum Grade of CECS)

Corequisite(s): CEG7030L

Enrollment Restrictions: Must be enrolled in one of the following levels: Graduate, Medical, Professional.

Course Level: Graduate
Schedule Type(s): Lecture

Grade Mode: Standard
An additional fee is associated with this course.